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| Design and Simulation of a
Modified Architecture of Carry Save Adder
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Full
text: |
 PDF(979.1KB) |
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Source |
International Journal of Engineering (IJE) |
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Table of Contents |
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Download
Complete Issue PDF(9.49MB) |
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Volume: 5 Issue: 1 |
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Pages: 1-175 |
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Publication
Date: March / April 2011 |
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ISSN
(Online): 1985-2312 |
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Pages |
102 - 113 |
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Author(s) |
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Published
Date |
04-04-2011 |
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Publisher |
CSC
Journals, Kuala Lumpur,
Malaysia |
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ADDITIONAL
INFORMATION |
| Keywords Abstract References Cited by Related Articles Collaborative
Colleague |
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KEYWORDS: Carry Save Adder, Synchronous Adder, Asynchronous Adder, VHDL Simulation |
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| This paper presents a technology-independent design and simulation of a modified architecture of the Carry-Save Adder. This architecture is shown to produce the result of the addition fast and by requiring a minimum number of logic gates. Binary addition is carried out by a series of XOR, AND and Shift-left operations. These operations are terminated with a completion signal indicating that the result of the addition is obtained. Because the number of shift operations carried out varies from 0 to n for n-bit addends, a behavioral model was developed in which all the possible addends having 2- to 15-bits were applied. A mathematical model was deducted from the data and used to predict the average number of shift required for standard binary numbers such as 32, 64 or 128-bits. 4-bit prototypes of this adder were designed and simulated in both synchronous and asynchronous modes of operation. |
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| 1 |
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| Chakib Alaoui : Colleagues
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