|
| HW/SW Partitioning Approach on Reconfigurable Multimedia System on Chip
|
|
Full
text: |
 PDF(376.3KB) |
|
|
Source |
International Journal of Engineering (IJE) |
|
Table of Contents |
|
|
Download
Complete Issue PDF(9.49MB) |
|
Volume: 5 Issue: 1 |
| |
Pages: 1-175 |
|
Publication
Date: March / April 2011 |
|
ISSN
(Online): 1985-2312 |
|
|
|
|
|
Pages |
62 - 72 |
|
Author(s) |
|
|
|
Published
Date |
04-04-2011 |
|
Publisher |
CSC
Journals, Kuala Lumpur,
Malaysia |
|
ADDITIONAL
INFORMATION |
| Keywords Abstract References Cited by Related Articles Collaborative
Colleague |
| |
|
| |
KEYWORDS: Partitioning, Profiling, Design Trotter |
|
|
| |
|
|
| This Manuscript is indexed in the following databases/websites:- |
|
| 1. Scribd |
| 2. refSeek |
| 3. Socol@r |
| 4. Google Scholar |
| 5. iSEEK |
| 6. Docstoc |
| 7. WorldCat |
| |
|
| |
|
|
| Due to the complexity and the high performance requirement of multimedia applications, the design of embedded systems is the subject of different types of design constraints such as execution time, time to market, energy consumption, etc. Some approaches of joint software/hardware design (Co-design) were proposed in order to help the designer to seek an adequacy between applications and architecture that satisfies the different design constraints. This paper presents a new methodology for hardware/software partitioning on reconfigurable multimedia system on chip, based on dynamic and static steps. The first one uses the dynamic profiling and the second one uses the design trotter tools. The validation of our approach is made through 3D image synthesis. |
| |
|
| |
|
| |
| 1 |
A .Baghdadi, exploration et conception systématique d’architectures multiprocesseur monopuces dédiées à des applications spécifiques, thèse PhD, Mai 2002, TIMA France.
|
|
|
| 2 |
D.Gajski, F.Vahid, S.Narayan and J.Gong System-level Exploration with SpecSyn. Design Automation Conference, Juin 1998.
|
|
|
| 3 |
H.J.Eikerling, W.HARDT, J.Gerlack, W.Rosenstiel: A Methodology for Rapid Analysis and optimization of Embedded Systems. International IEEE Symposium and workshop on ECBS, D-friedrichshafen, Mars 1996
|
|
|
| 4 |
J.Grode and J.Madsen Performance Estimation for Hardware/Software Codesign using Hierarchical Colored Petri Nets. Proceedings of Jigh Performance Computing’98, in Special Session on Petri Net Applications and HPC, Boston, Avril 1998.
|
|
|
| 5 |
J.henkel and R. Emst, High-level Estimation Techniques for usage in hardware/software codesign. Asia and south Pasific Automation Conference Yokohama, Japan, Fevrier 1998
|
|
|
| 6 |
J.Liu, M.Lajolo and A.Sangiovanni-Vincentelli, Software Timing Analysis Using HW/SW Cosimulation and Instruction Set Simulator. International Workshop on Hardware-Software Codesign, Mars 1998.
|
|
|
| 7 |
T-Y.Yen and W.Wolf, Communication Synthesis for Distributed Embedded Systems. International Conference on Computer-Aided Design,1995.
|
|
|
| 8 |
S. Rouxel Modélisation et Caractérisation de Plates-Formes SoC Hétérogènes : Application
|
|
|
| 9 |
Y.le moullec, J.P.Diguet, N. Ben amor, T.gourdeaux, and J.L.Philippe: Algorithmic-level Specification and Characterization of Embedded Multimedia Applications with Design Trotter. Journal of VLSI Signal Processing 42, 185–208, 2006
|
|
|
| 10 |
N. Ben Amor, Y. Le Moullecc, J. P. Diguet, J.L. Philippe, M.Abid: Design of a multimedia processor based on metrics computation. Advances in Engineering Software 36 (2005) 448–458
|
|
|
| 11 |
S. Wuytack, J.P. Diguet, F. Catthoor, H. De Man. Formalized methodology for data reuse exploration for low-power hierarchical memory mappings. IEEE Trans VLSI Syst 1998;6(4):529–37.
|
|
|
| 12 |
K. Bertels, G. Kuzmanov, E. M. Panainte, G. N. Gaydadjiev, Y. D. Yankova, V. Sima, K. Sigdel, R. J. Meeuws, and S. Vassiliadis, “Profiling, compilation, and hdl generation within the hartes project,” in FPGAs and Reconfigurable Systems: Adaptive Heterogeneous Systemson- Chip and European Dimensions (DATE 07 Workshop), April 2007, pp. 53–62.
|
|
|
| 13 |
A. Srivastava and A. Eustace, “Atom: a system for building customized program analysis tools,” SIGPLAN Not., vol. 39, no. 4, pp. 528–539, 2004.
|
|
|
| 14 |
R. J. Meeuws, Y. D. Yankova, K. Bertels, G. N. Gaydadjiev, and S. Vassiliadis, “A quantitative prediction model for hardware/software partitioning,” in Proceedings of 17th International Conference on Field Programmable Logic and Applications (FPL07), August 2007, p. 5.
|
|
|
| |
|
| |
|
| |
| |
|
| |
|
| |
| |
|
| |
|
| |
|
| Kais Loukil : Colleagues
|
|
| Nader Ben Amor : Colleagues
|
|
| Mohamed Abid : Colleagues
|
|
