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| Design of an Analog CMOS based Interval Type-2 Fuzzy Logic Controller Chip
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Source |
International Journal of Artificial Intelligence and Expert Systems (IJAE) |
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Table of Contents |
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Complete Issue PDF(1.8MB) |
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Volume: 2 Issue: 4 |
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Pages: NULL |
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Publication
Date: September / October 2011 |
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ISSN
(Online): 2180-124X |
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Pages |
167 - 183 |
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Author(s) |
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Published
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05-10-2011 |
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Publisher |
CSC
Journals, Kuala Lumpur,
Malaysia |
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ADDITIONAL
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| Keywords Abstract References Cited by Related Articles Collaborative
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KEYWORDS: Type-2 fuzzy logic Systems, interval type-2 fuzzy Logic Systems, Footprint of Uncertainty, CMOS, Current Mirror |
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| We propose the design of an analog Interval Type-2 (IT2) fuzzy logic controller chip that is based on the realization approach of averaging of two Type-1 Fuzzy Logic Systems (T1 FLSs). The fuzzifier is realized using transconductance mode membership function generator circuits. The membership functions are made tunable by setting some reference voltages on the IC pins. The inference is realized using current mode MIN circuits. The consequents are also tunable by providing five reference current sources on chip. Defuzzification of both the T1 FLSs is based on weighted average method realized through scalar and multiplier-divider circuits. An analog current-mode averager circuit is used for obtaining the defuzzified output of the IT2 fuzzy logic controller chip. The chip is designed for two inputs, one output and nine tunable fuzzy rules and is realized in 0.18 µm technology. Cadence Virtuoso Schematic/Layout Editor has been used for the chip design and the performances of all the circuits are confirmed through the simulations carried out using Cadence Spectre tool. The proposed architecture has an operation speed of 20 MFLIPS and a power consumption of 20mW. The whole chip occupies an area of 0.32 mm2. |
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| Mamta Khosla : Colleagues
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| Rakesh Kumar Sarin : Colleagues
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| Moin Uddin : Colleagues
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