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| System-Level Modeling of a Network-on-Chip
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Full
text: |
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Source |
International Journal of Computer Science and Security (IJCSS) |
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Table of Contents |
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Complete Issue PDF(3.33MB) |
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Volume: 3 Issue: 3 |
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Pages: 154-271 |
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Publication
Date: June 2009 |
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ISSN
(Online): 1985-1553 |
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Pages |
154 - 174 |
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Author(s) |
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Published
Date |
01-09-2009 |
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Publisher |
CSC
Journals, Kuala Lumpur,
Malaysia |
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ADDITIONAL
INFORMATION |
| Keywords Abstract References Cited by Related Articles Collaborative
Colleague |
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KEYWORDS: SMNN, SMFFNN, Training, Epoch, Preprocessing, Pre-training |
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| This paper presents the system-level modeling and simulation of a concurrent architecture for a customizable and scalable network-on-chip (NoC), using system level tools (MLDesigner). MLDesigner supports the integration of heterogeneous models of computation, which provide a framework to model various algorithms and activities, while accounting for and exploiting concurrency and synchronization aspects. Our methodology consists of three main phases: system-level concurrency modeling, component-level modeling, and system-level integration. At first, the Finite State Processes (FSP) symbolic language is used to model and analyze the system-level concurrency aspects of the NoC. Then, each component of the NoC is abstracted as a customizable class with parameters and methods, and instances of these classes are used to realize a 4×4 mesh-based NoC within the MLDesigner environment. To illustrate and validate the system-level operation of the NoC, we provide simulation results for various scheduling criteria, injection rates, buffer sizes, and network traffic patterns. |
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TechRepublic
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| Ankur Agarwal : Colleagues
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