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| A Simple Design to Mitigate Problems of Conventional Digital Phase Locked Loop
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Full
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 PDF(183.6KB) |
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Source |
Signal Processing: An International Journal (SPIJ) |
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Table of Contents |
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Download
Complete Issue PDF(5.42MB) |
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Volume: 6 Issue: 2 |
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Pages: NULL |
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Publication
Date: April 2012 |
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ISSN
(Online): 1985-2339 |
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Pages |
65 - 77 |
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Author(s) |
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Published
Date |
16-04-2012 |
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Publisher |
CSC
Journals, Kuala Lumpur,
Malaysia |
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ADDITIONAL
INFORMATION |
| Keywords Abstract References Cited by Related Articles Collaborative
Colleague |
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KEYWORDS: Teager Energy Operator, Wavelet Packet Transform, Statistical Modeling, Thrsholding Function |
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| This paper presents a method which can estimate frequency, phase and power of received signal corrupted with additive white Gaussian noise (AWGN) in large frequency offset environment. Proposed method consists of two loops, each loop is similar to a phase–locked loop (PLL) structure. The proposed structure solves the problems of conventional PLL such as limited estimation range, long settling time, overshoot, high frequency ripples and instability. Traditional inability of PLL to synchronize signals with large frequency offset is also removed in this method. Furthermore, proposed architecture along with providing stability, ensures fast tracking of any changes in input frequency. Proposed method is also implemented using field programmable gate array (FPGA), it consumes 201 mW and works at 197 MHz. |
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| 1 |
J. G. Proakis, M. Salehi, Digital Communications, Mcgraw-Hill, 2008.
|
|
|
| 2 |
Y. Wang, Y. Zhang, Z. Yang, “Parallel Carrier Recovery in All-Digital Receiver,” in Proc. WICOM, pp. 1-4, 2009.
|
|
|
| 3 |
G. Karam, J. Kervarec, H. Sari, P. Vandamme, ”All-digital implementation of the carrier recovery loop in digital radio systems,” International Conference on Communications, pp. 175- 179, 1991.
|
|
|
| 4 |
M. Padua, S. Deckmann, G. Sperandio, F. Marafao, D. Colon “Comparative analysis of Synchronization Algorithms based on PLL, RDFT and Kalman Filter,” IEEE International Symposium on Industrial Electronics, pp. 964-970, 2007.
|
|
|
| 5 |
Y. Linn,” Robust M-PSK phase detectors for carrier synchronization PLLs in coherent receivers: theory and simulations ,” IEEE Transactions on Communications, Vol. 57, pp. 1794-1805, 2009.
|
|
|
| 6 |
K. Lim, S. Choi, B. Kim , ” Optimal loop bandwidth design for low noise PLL applications,” Proceedings of the ASP-DAC '97, pp. 425-428,1997.
|
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| 7 |
J. Roche, W. Rahadjandrabey, L. Zady, G. Bracmard, D. Fronte, “A PLL with loop bandwidth enhancement for low-noise and fast-settling clock recovery,” In Proc. of Electronics, circuits and systems IEEE conference, pp. 802-805, 2008.
|
|
|
| 8 |
W. Ping-Ying, Fu. Chia-Huang, ”All digital modulation bandwidth extension technique for narrow bandwidth analog fractional-N PLL,” in Proc. of ESSCIR, pp. 270-273, 2010.
|
|
|
| 9 |
A. Carlosena, A. Manuel- Lazaro, “Design of Higher-Order Phase-Lock Loops,” IEEE Transaction on Circuits and systems II, vol. 54, pp. 9-13, 2007.
|
|
|
| 10 |
S. Changhong, C. Zhongze, Z. Lijun, L. Yong, “Design and Implementation of Bandwidth Adaptable Third-order All digital Phase-Locked Loops,” in Proc. WICOM, pp.1-4, 2010.
|
|
|
| 11 |
X. hongbing, G. Peiyuan, L. Shiyi, “Modeling and simulation of Higher-order PLL rotation tracking system in GNSS receiver,” in Proc. ICMA, 2009, pp. 1128-1133.
|
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| 12 |
P. Hanumolu, “W Gu-Yeon, M. un-ku, A Wide- Tracking Range clock and Data recovery Circuit,” IEEE Transaction on Solid state circuits, vol. 43, pp. 425-439, 2008.
|
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| 13 |
D. Green. “Lock-In, Tracking, and acquisition of AGC-aided phase-locked loops,” IEEE Transaction on Ciruits and Systems, vol. 32, pp. 559-568, 1985.
|
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| 14 |
L. Verrazzani, “ Pull-In Time and Range of Any Order Generalized PLL.” IEEE Transaction on Aerospace and Electronic systems, Vol. AES14, pp.329-333, 2007.
|
|
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| 15 |
P. Hanumolu, “W Gu-Yeon, M. un-ku, A Wide- Tracking Range clock and Data recovery Circuit,” IEEE Transaction on Solid state circuits, vol. 43, pp. 425-439, 2008.
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| 16 |
M. Saber, M.T.A. Khan, Y. Jitsumatsu, “Frequency and Power Estimator for Digital Receivers in Doppler Shift environment.'' Signal Processing: An international journal (SPIJ), vol. 5, pp. 192-208, Dec. 2011.
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| 17 |
M. Saber, Y. Jitsumatsu, M.T.A. Khan, “Design and Implementation of Low Ripple Low Power Digital Phase-Locked Loop.'' Signal Processing: An international journal (SPIJ), vol. 4, pp. 304-317, Feb. 2011.
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| 18 |
P. Pong Chu. RTL Hardware Design Using VHDL: Coding for Efficiency, Portability and Scalability. Wiley-IEEE Press, 2006.
|
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|
| 19 |
Xilinx Inc. system generator for DSP user guide. Xilinx, 2009.
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|
| 20 |
W.Y. Yang. Matlab/Simulink for digital communication. A-Jin, 2009.
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| 21 |
Pong p. chu. FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version. Wiley- Interscience, 2008.
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| Mohamed Saber Saber Elsayes : Colleagues
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| Yutaka Jitsumatsu : Colleagues
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| Mohamed tahir Abasi Khan : Colleagues
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