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Hardware Architecture of Complex K-best MIMO Decoder
Mehnaz Rahman, Gwan S. Choi
Pages - 56 - 68     |    Revised - 31-03-2016     |    Published - 30-04-2016
Volume - 10   Issue - 1    |    Publication Date - April 2016  Table of Contents
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KEYWORDS
Complex K-best Algorithm, MIMO, Lattice Reduction, SE Enumeration, VLSI Architecture.
ABSTRACT
This paper presents a hardware architecture of complex K-best Multiple Input Multiple Output (MIMO) decoder reducing the complexity of Maximum Likelihood (ML) detector. We develop a novel low-power VLSI design of complex K-best decoder for MIMO and 64 QAM modulation scheme. Use of Schnorr-Euchner (SE) enumeration and a new parameter, Rlimit in the design reduce the complexity of calculating K-best nodes to a certain level with increased performance. The total word length of only 16 bits has been adopted for the hardware design limiting the bit error rate (BER) degradation to 0.3 dB with list size, K and Rlimit equal to 4. The proposed VLSI architecture is modeled in Verilog HDL using Xilinx and synthesized using Synopsys Design Vision in 45 nm CMOS technology. According to the synthesize result, it achieves 1090.8 Mbps throughput with power consumption of 782 mW and latency of 0.33 us. The maximum frequency the design proposed is 181.8 MHz.
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Miss Mehnaz Rahman
Department of ECE Texas A&M University - United States of America
mehnaz.rahman.eee@gmail.com
Dr. Gwan S. Choi
Department of ECE Texas A&M University - United States of America