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Design and Simulation of a Modified Architecture of Carry Save Adder
Chakib Alaoui
Pages - 102 - 113     |    Revised - 31-03-2011     |    Published - 04-04-2011
Volume - 5   Issue - 1    |    Publication Date - March / April 2011  Table of Contents
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KEYWORDS
Carry Save Adder, Synchronous Adder, Asynchronous Adder, VHDL Simulation
ABSTRACT
This paper presents a technology-independent design and simulation of a modified architecture of the Carry-Save Adder. This architecture is shown to produce the result of the addition fast and by requiring a minimum number of logic gates. Binary addition is carried out by a series of XOR, AND and Shift-left operations. These operations are terminated with a completion signal indicating that the result of the addition is obtained. Because the number of shift operations carried out varies from 0 to n for n-bit addends, a behavioral model was developed in which all the possible addends having 2- to 15-bits were applied. A mathematical model was deducted from the data and used to predict the average number of shift required for standard binary numbers such as 32, 64 or 128-bits. 4-bit prototypes of this adder were designed and simulated in both synchronous and asynchronous modes of operation.
CITED BY (1)  
1 Tripathy, S., Prakash, L. B. O. M., Patro, B. S., & Mandal, S. K. (2013). A comparative analysis of different 8-bit adder topologies at 45 nm technology. International journal of engineering research and technology, 2(10).
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Dr. Chakib Alaoui
University of Massachusetts / Taif University - Saudi Arabia
Chakib_Alaoui@yahoo.com