Home   >   CSC-OpenAccess Library   >    Manuscript Information
Full Text Available

(979.05KB)
This is an Open Access publication published under CSC-OpenAccess Policy.

PUBLICATIONS BY COUNTRIES

Top researchers from over 74 countries worldwide have trusted us because of quality publications.

United States of America
United Kingdom
Canada
Australia
Malaysia
China
Japan
Saudi Arabia
Egypt
India
Design and Simulation of a Modified Architecture of Carry Save Adder
Chakib Alaoui
Pages - 102 - 113     |    Revised - 31-03-2011     |    Published - 04-04-2011
Volume - 5   Issue - 1    |    Publication Date - March / April 2011  Table of Contents
MORE INFORMATION
KEYWORDS
Carry Save Adder, Synchronous Adder, Asynchronous Adder, VHDL Simulation
ABSTRACT
This paper presents a technology-independent design and simulation of a modified architecture of the Carry-Save Adder. This architecture is shown to produce the result of the addition fast and by requiring a minimum number of logic gates. Binary addition is carried out by a series of XOR, AND and Shift-left operations. These operations are terminated with a completion signal indicating that the result of the addition is obtained. Because the number of shift operations carried out varies from 0 to n for n-bit addends, a behavioral model was developed in which all the possible addends having 2- to 15-bits were applied. A mathematical model was deducted from the data and used to predict the average number of shift required for standard binary numbers such as 32, 64 or 128-bits. 4-bit prototypes of this adder were designed and simulated in both synchronous and asynchronous modes of operation.
CITED BY (1)  
1 Tripathy, S., Prakash, L. B. O. M., Patro, B. S., & Mandal, S. K. (2013). A comparative analysis of different 8-bit adder topologies at 45 nm technology. International journal of engineering research and technology, 2(10).
1 Google Scholar 
2 CiteSeerX 
3 refSeek 
4 iSEEK 
5 Socol@r  
6 Scribd 
7 WorldCat 
8 SlideShare 
9 PdfSR 
1 Bruce Gilchrist, J. H. Pomerene, and S. Y. Wong, “Fast Carry Logic for Digital Computers,” IRE Transactions on Electronic Computers, vol. EC-4, pp. 133-136, 1955.
2 E.E. SwartZlander, “Computer Arithmetic”, volume I, IEEE computer society press, 1990
3 I. Koren, “Computer arithmetic algorithms”, Prentice-Hall, 1993
4 F.C Cheng, S. H. Unger, “Self-Timed Carry-Look Ahead Adders”, IEEE Transactions on Computers, Vol. 49, No. 7, July 2000
5 M. Alioto, G. Palumbo, “Analysis and Comparison on Full Adder Block in Submicron Technology”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 6, December 2002
6 M. D. Ercegovac, T. Lang, “Digital Arithmetic”, Morgan Kaufmann Publishers. An imprint of Elsevier Science, 2004.
7 B. Parhami, “Computer Arithmetic, Algorithm and Hardware Design”, Oxford University Press, New York, pp. 91-119, 2000.
8 R. P. P. Singh, P. Kumar, B. Singh, “Performance Analysis of 32-bit Array Multiplier with a Carry Save Adder and with a Carry Look Ahead Adder”, International Journal of Recent Trends in Engineering, Vol. 2, No. 6, November 2009.
9 T. Kim, W. Jao, and S. Tjiang, “Arithmetic optimization using carry-save-adders”, in Proc. Design Automation Conf., Jun. 1998, pp. 433–438.
10 T. Kim and J. Um, “A timing-driven synthesis of arithmetic circuits using carry-save-adders”, in Proc. Asia and South Pacific Design Automation Conf., Jan. 2000, pp. 313–316.
11 Y. Kim and T. Kim, “An accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save adder cells”, in Proc. Midwest Symposium on Circuit and Systems, Aug. 2000.
12 T. Kim, W. Jao,an d S. Tjiang,“Circuit Optimization using Carry-Save-Adder Cells”, IEEE TCAD, October 1998.
13 J. Um, T. Kim, C. L. Liu, “Optimal Allocation of Carry-Save-Adders in Arithmetic Optimization”, Proc. ICCAD, 1999.
14 B.Ramkumar, H. M Kittur, P.Mahesh Kannan, “ASIC implementation of Modified Faster Carry Save Adder”. European Journal of Scientific Research. ISSN 1450-216X, Vol.42 No.1, 2010, pp.53-58.
Dr. Chakib Alaoui
University of Massachusetts / Taif University - Saudi Arabia
Chakib_Alaoui@yahoo.com