Home   >   CSC-OpenAccess Library   >    Manuscript Information
Full Text Available

(119.11KB)
This is an Open Access publication published under CSC-OpenAccess Policy.
Extremely Low Power FIR Filter for a Smart Dust Sensor Module
Md. Moniruzzaman, Md. Murad Kabir Nipun, Sajib Roy
Pages - 178 - 183     |    Revised - 15-05-2012     |    Published - 20-06-2012
Volume - 6   Issue - 3    |    Publication Date - June 2012  Table of Contents
MORE INFORMATION
KEYWORDS
STSCL, PDP, CMOS, CSD Multiplier, FIR filter
ABSTRACT
Digital filters are common components in many applications today, also in for sensor systems, such as large-scale distributed smart dust sensors. For these applications the power consumption is very critical, it has to be extremely low. With the transistor technology scaling becoming more and more sensitive to e.g. gate leakage, it has become a necessity to find ways to minimize the flow of leakage in current CMOS logic. This paper studies sub-threshold source coupled logic (STSCL) in a 45-nm process. The STSCL can be used instead of traditional CMOS to meet the low power and energy consumption requirements. The STSCL style is in this paper used to design a digital filter, applicable for the audio interface of a smart dust sensor where the sample frequency will be 44.1 kHz. A finite-length impulse response (FIR) filter is used with transposed direct form structure and for the coefficient multiplication five-bit canonic signed digit [7] based serial/parallel multipliers were used. The power consumption is calculated along with the delay in order to present the power delay product (PDP) such that the performance of the sub-threshold logic can be compared with corresponding CMOS implementation. The simulated results shows a significant reduction in energy consumption (in terms of PDP) with the system running at a supply voltage as low as 0.2 V using STSCL.
CITED BY (1)  
1 Elbanhawi, M., & Simic, M. (2013, February). Robotics application in remote data acquisition and control for solar ponds. In Applied Mechanics and Materials (Vol. 253, pp. 705-715).
1 Google Scholar
2 CiteSeerX
3 refSeek
4 Scribd
5 SlideShare
6 PdfSR
1 S. Kim, S. Kosonocky, D. Knebel, and K.Stawiasz, “Experimental measurement of a novel power gating structure with intermidiate power saving mode”, In proceedings of ISPLED, pp. 20-25, August 2004.
2 S. Kosonocky, M. Immediato, P. Cottrell, T. Hook, R. Mann, and J.Brown, “Enhanced multi threshold (MTCMOS) circuits using variable well bias”, In proceedings of ISLPED, pp. 165- 169, Aug. 2001.
3 H. Soeleman, K. Roy, and C.Paul, “Robust subthreshodl logic for ultra-low power operation”. In IEEE transactions on Very Large Scale Integration (VLSI) Systems, Issue: 1, Vol: 9, pp. 90-99, February 2001.
4 A. Tajalli, E. J. Brauer, Y. Leblebici, E. Vittoz, “Sub-threshold Source Coupled Logic Circuits for Ultra-Low Power Applications”, in IEEE Journal of Solid-State Circuits, Vol. 43, No. 7, pp. 1699-1710, 2008.
5 S. Sunder, F. El-guibaly, and A. Antoniou, "Two’s complement fast serial-parallel multiplier," In Proceedings of IEE Proceedings of Circuits, Devices and Systems, Issue:1, vol: 142, pp. 41-44, February 1995
6 M. Vesterbacka, K. Palmkvist, and L. Wanhammar, "Realization of Serial/Parallel Multipliers with Fixed Coefficients," In Proceedings of National Conf. on Radio Science, RVK'93, Lund Institute of Technology, Lund, Sweden, pp. 209-212, 5-7 April 1993.
7 M. Hasan, J. Karam, M. Falkinburg, A Helwig and M. Ronning, "Canonic signed digit FIR filter design," In Proceedings of 34th Asilomar Conference on Signals, Systems and Computer, vol: 2, pp. 1653-1656, 29 October 2000.
Mr. Md. Moniruzzaman
- Bangladesh
Mr. Md. Murad Kabir Nipun
- Bangladesh
Mr. Sajib Roy
World University of Bangladesh - Bangladesh
sajro823@student.liu.se