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Frequency and Power Estimator for Digital Receivers in Doppler Shift Environments
M. Saber, M. T. A. Khan, Y. Jitsumatsu
Pages - 185 - 202     |    Revised - 01-11-2011     |    Published - 15-12-2011
Volume - 5   Issue - 5    |    Publication Date - November / December 2011  Table of Contents
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KEYWORDS
Digital Phase Locked Loop (DPLL), Frequency Estimator, FPGA
ABSTRACT
A frequency estimator well suited for digital receivers is proposed. Accurate estimates of unknown frequency and power of input sinusoidal signal, in the presence of additive white Gaussian noise (AWGN), are provided. The proposed structure solve the problems of traditional phase locked loop (PLL) such as, narrow tracking range, overshoot, long settle time, double frequency ripples in the loop and stability. Proposed method can estimate frequencies up to half the sampling frequency irrespective of the input signal power. Furthermore, it provides stability and allows fast tracking for any changes in input frequency. The estimator is also implemented using field programmable gate array (FPGA), consumes 127 mW and works at a frequency of 225 MHz. Proposed method can estimate the fluctuation in frequency of transmitter’s oscillator, can be used as a frequency shift keying receiver and can also be applied as a digital receiver in Doppler shift environment.
CITED BY (1)  
1 Sarkar, S., Maulik, U., & Biswas, B. (2013). Performance of a new split digital phase lock loop in additive wideband Gaussian noise. International Journal of Adaptive Control and Signal Processing, 27(12), 1107-1117.
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Mr. M. Saber
Kyushu university - Japan
mohsaber1@yahoo.com
Associate Professor M. T. A. Khan
Ritsumeikan Asia Pacific university - Japan
Associate Professor Y. Jitsumatsu
Kyushu university - Japan