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Design of High Speed Low Power 15-4 Compressor Using Complementary Energy Path Adiabatic Logic
K.V.S.S. Aditya, Chenna Sai Prabhakar Rao, Satya Aditya Praneeth Emani
Pages - 77 - 87     |    Revised - 10-11-2014     |    Published - 10-12-2014
Volume - 8   Issue - 5    |    Publication Date - December 2014  Table of Contents
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KEYWORDS
Compressor, Static Adiabatic Logic, CEPAL (Complementary Energy Path Adiabatic Logic), Multi-phase Power-clocked Adiabatic Circuits.
ABSTRACT
This paper presents the implementation of a novel high speed low power 15-4 Compressor for high speed multiplication applications using single phase clocked quasi static adiabatic logic namely CEPAL (Complementary Energy Path Adiabatic Logic). The main advantage of this static adiabatic logic is the minimization of the 1/2CVth2 energy dissipation occurring every cycle in the multi-phase power-clocked adiabatic circuits. The proposed Compressor uses bit sliced architecture to exploit the parallelism in the computation of sum of 15 input bits by five full adders. The newly proposed Compressor is also centered around the design of a novel 5-3 Compressor that attempts to minimize the stage delays of a conventional 5-3 Compressor that is designed using single bit full adder and half adder architectures. Firstly, the performance characteristics of CEPAL 15-3 Compressor with 14 transistor and 10 transistor adder designs are compared against the conventional static CMOS logic counterpart to identify its adiabatic power advantage. The analyses are carried out using the industry standard Tanner EDA design environment using 250 nm technology libraries. The results prove that CEPAL 14T 15-4 Compressor is 68.11% power efficient, 75.31% faster over its static CMOS counterpart.
1 Google Scholar 
2 CiteSeerX 
3 refSeek 
4 Scribd 
5 SlideShare 
6 PdfSR 
1 Neil H. E. Weste, David Harris, Ayan Banerjee, “CMOS VLSI Design-A Circuits and Systems Perspective,” Pearson Education, ISBN 978-81-7758-568-1, pp. 129-134.
2 Kiat-Seng Yeo, Samir S. Rofail, Wang-Ling Goh, “CMOS/BiCMOS ULSI: low voltage, low power,” Pearson Education, ISBN 978-81-317-0826-2, pp. 3-8, pp. 496-508.
3 S. Kim, C. H. Ziesler, and M. C. Papaefthymiou, “Charge-recovery computing on silicon,” IEEE Trans. Computers, vol. 54, no. 6, pp. 651–659, June 2005.
4 J. Marjonen, and M. Aberg, “A single clocked adiabatic static logic – a proposal for digital low power applications,” J. VLSI Signal Processing, vol. 27, no. 27, pp. 253–268, Feb. 2001.
5 V. I. Starosel’skii, “Adiabatic logic circuits: A review,” Russian Micro- electronics, vol. 31, no. 1, pp. 37–58, 2002.
6 K. A. Valiev and V. I. Starosel’skii, “A model and properties of a thermodynamically reversible logic gate,” Mikroelektronika, vol. 29, no. 2, pp.83–98, 2000.
7 V. I. Starosel’skii, “Reversible logic,” Mikroelektronika, vol. 28, no. 3, pp. 213–222, 1999.
8 N. Anuar, Y. Takahashi and T. Sekine, “Adiabatic logic versus CMOS for low power applications,” Proc. ITC–CSCC, pp. 302–305, Jul. 2009.
9 Jan Rabaey & Massoud Pedram, “Low power Design methodologies,” Springer Publication, 1995.
10 C. Baugh, B. Wooley, “A two’s complement parallel array multiplication algorithm”, IEEE Transactions on Computers, Vol. C-22, No. 12, 1973, pp. 1045-1047.
11 J. Gu, C. Chang, “Ultra low voltage low power 4-2 Compressor for high speed multiplications”, Proc. of IEEE Int. Symp. Circuits and Systems”, Vol. 5, 2003, pp. 321-324.
12 L. Junming, S. Yan, L. Zhengui, W. Ling, “A novel 10 transistor low power high speed full adder cell“, Proc. 6th Int. Conf. on Solid State and Integrated Circuit Technology, Vol. 1, pp. 1155-1158.
13 A. M. Shams, M. Bayoumi, “A novel high performance CMOS 1 bit full adder cell”, IEEE Trans. on Circuits and Systems II, Analog and Digital Signal Processing, Vol. 47, No. 5, pp. 478-481, 2000.
Mr. K.V.S.S. Aditya
Electronics and Communication Engineering GITAM University Hyderabad , 502329 - India
katam.aditya@gmail.com
Mr. Chenna Sai Prabhakar Rao
Electronics and Communication Engineering Mahatma Gandhi Institute of Technology Hyderabad , 500075 - India
Mr. Satya Aditya Praneeth Emani
Electronics and Communication En gineering GITAM University Vishakapatnam , 530045 - India