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A Low Power Digital Phase Locked Loop With ROM-Free Numerically Controlled Oscillator
Mohamed Saber Saber Elsayes, Yutaka Jitsumatsu, Mohamed tahir Abasi Khan
Pages - 142 - 155     |    Revised - 01-09-2011     |    Published - 05-10-2011
Volume - 5   Issue - 4    |    Publication Date - September / October 2011  Table of Contents
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KEYWORDS
Digital Phase Locked Loop (DPLL), Field Programmable Gate Array (FPGA), Software Defined Radio (SFDR), Read Only Memory (ROM), Spurious Free Dynamic Range (SFDR)
ABSTRACT
The objective of this paper is to explore the analysis and design of second order digital phase-locked loop (DPLL), and present low power architecture for DPLL. The proposed architecture aims to reduce the high power consumption of DPLL, which results from using a read only memory (ROM) in implementation of the numerically controlled oscillator (NCO). The proposed DPLL utilizes a new design for NCO, in which no ROM is used. DPLL is deigned and implemented using FPGA, consumed 237 mw, which saves more than 25% of power consumption, and works at faster clock frequency compared to traditional architecture.
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Mr. Mohamed Saber Saber Elsayes
Kyushu university - Japan
mohsaber1@yahoo.com
Associate Professor Yutaka Jitsumatsu
- Japan
Associate Professor Mohamed tahir Abasi Khan
Ritsumeikan Asia Pacific university - Japan