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Design and Implementation of Low Ripple Low Power Digital Phase-Locked Loop
M. Saber, Yutaka Jitsumatsu, Mohamed Tahit Khan
Pages - 304 - 317     |    Revised - 31-01-2011     |    Published - 08-02-2011
Volume - 4   Issue - 6    |    Publication Date - January / February  Table of Contents
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KEYWORDS
Digital Phase-Locked Loop (DPLL),, Field Programmable Gate Array (FPGA),, Numerically-controlled Oscillator (NCO), , Read Only Memory (ROM),
ABSTRACT
We propose a phase-locked loop (PLL) architecture, which reduces the double frequency ripple without increasing the order of loop filter. Proposed architecture uses quadrature numerically–controlled oscillator (NCO) to provide two output signals with phase difference of π/2. One of them is subtracted from the input signal before multiplying with the other output of NCO. The system also provides stability in case the input signal has noise in amplitude or phase. The proposed structure is implemented using field programmable gate array (FPGA), which dissipates 15.44mw and works at clock frequency of 155.8 MHz.
CITED BY (1)  
1 Zhu, W. J., Feng, Y., Huang, M., Li, T. H., & Mao, F. C. (2013, December). An improved PLL and its performance simulation. In Applied Mechanics and Materials (Vol. 427, pp. 1557-1562).
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Mr. M. Saber
KYUSHU UNIVERSITY - Japan
mohsaber1@yahoo.com
Associate Professor Yutaka Jitsumatsu
KYUSHU UNIVERSITY - Japan
Associate Professor Mohamed Tahit Khan
Ritsumeikan Asia Pacific University - Japan