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System-Level Modeling of a Network-on-Chip
Ankur Agarwal
Pages - 154 - 174     |    Revised - 05-08-2009     |    Published - 01-09-2009
Volume - 3   Issue - 3    |    Publication Date - June 2009  Table of Contents
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KEYWORDS
SMNN, SMFFNN, Training, Epoch, Preprocessing, Pre-training
ABSTRACT
This paper presents the system-level modeling and simulation of a concurrent architecture for a customizable and scalable network-on-chip (NoC), using system level tools (MLDesigner). MLDesigner supports the integration of heterogeneous models of computation, which provide a framework to model various algorithms and activities, while accounting for and exploiting concurrency and synchronization aspects. Our methodology consists of three main phases: system-level concurrency modeling, component-level modeling, and system-level integration. At first, the Finite State Processes (FSP) symbolic language is used to model and analyze the system-level concurrency aspects of the NoC. Then, each component of the NoC is abstracted as a customizable class with parameters and methods, and instances of these classes are used to realize a 4×4 mesh-based NoC within the MLDesigner environment. To illustrate and validate the system-level operation of the NoC, we provide simulation results for various scheduling criteria, injection rates, buffer sizes, and network traffic patterns.
CITED BY (9)  
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8 S. J. Aboud, “Secure E-payment Protocol”, International Journal of Security (IJS), 3(5), pp. 85 – 92, 2009.
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Dr. Ankur Agarwal
- United States of America
ankur@cse.fau.edu