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Area Efficient and Reduced Pin Count Multipliers
Omar Nibouche
Pages - 1 - 9 | Revised - 15-01-2013 | Published - 28-02-2013
Published in International Journal of Engineering (IJE)
MORE INFORMATION
KEYWORDS
Reduced Pin Count, Serial Multiplication, Area-Time2
ABSTRACT
Fully serial multipliers can play an important role in the implementation of DSP algorithms in
resource-limited chips such as FPGAs; offering area efficient architectures with a reduced pin
count and moderate throughput rates. In this paper two structures that implement the fully serial
multiplication operation are presented. One significant aspect of the new designs is that they are
systolic and require near communication links only. They are superior in speed and area usage to
similar architectures in the literature. The paper also present a new fully serial multiplier optimized
for area-time2 efficiency with better performance than available architectures in the open
literature.
| 1 | Google Scholar  |
| 2 | CiteSeerX |
| 3 | refSeek |
| 4 | Scribd |
| 5 | SlideShare |
| 6 | PdfSR |
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| A. Aggoun, A.S. Ashur, and M.K. Ibrahim, “Area-Time efficient serial-serial multipliers”,IEEE International Symp. On Circuits and Systems (ISCAS), pp.V-585-588, GENEVA, May 2000. | |
| A.S. Ashur, “New Efficient Multiplication Structure and their Applications”. Ph.D. thesis, Dept.of Electrical and Electronic Eng., the University of Nottingham, 1996. | |
| J. Scanlon and W. Fuchs, “'High-performance bit-serial multiplication”, in Proc. IEEE ICCD'86,Rye Brook, NY, Oct. 1986. | |
| K.K. Parhi, "VLSI Digital Signal Processing Systems: Design and Implementation", A WileyInterscience Publication, 1999. | |
| N. Strader and V. Rhyne, “A canonical bit-sequential multiplier”, IEEE Trans. Computer, 1982,vol. 31, pp. 691-626. | |
| P. Ienne, and M. Viredaz, “A bit-serial multipliers and squarers”, IEEE Trans. Computer, 1994,43, (12), pp.1445-1450. | |
Dr. Omar Nibouche
Taif University - Saudi Arabia
o.nibouche@tu.edu.sa
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