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A Simple Design to Mitigate Problems of Conventional Digital Phase Locked Loop
Mohamed Saber Saber Elsayes, Yutaka Jitsumatsu, Mohamed tahir Abasi Khan
Pages - 65 - 77     |    Revised - 15-03-2012     |    Published - 16-04-2012
Volume - 6   Issue - 2    |    Publication Date - April 2012  Table of Contents
Teager Energy Operator, Wavelet Packet Transform, Statistical Modeling, Thrsholding Function
This paper presents a method which can estimate frequency, phase and power of received signal corrupted with additive white Gaussian noise (AWGN) in large frequency offset environment. Proposed method consists of two loops, each loop is similar to a phase–locked loop (PLL) structure. The proposed structure solves the problems of conventional PLL such as limited estimation range, long settling time, overshoot, high frequency ripples and instability. Traditional inability of PLL to synchronize signals with large frequency offset is also removed in this method. Furthermore, proposed architecture along with providing stability, ensures fast tracking of any changes in input frequency. Proposed method is also implemented using field programmable gate array (FPGA), it consumes 201 mW and works at 197 MHz.
CITED BY (2)  
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2 Zhu, W. J., Feng, Y., Huang, M., Li, T. H., & Mao, F. C. (2013, December). An improved PLL and its performance simulation. In Applied Mechanics and Materials (Vol. 427, pp. 1557-1562).
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Dr. Mohamed Saber Saber Elsayes
Kyushu university - Japan
Associate Professor Yutaka Jitsumatsu
Kyushu university - Japan
Associate Professor Mohamed tahir Abasi Khan
Ritsumeikan Asia Pacific university - Japan

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